I have made myself a phase locked loop (PLL) using my cyclone iv FPGA
Here is what I did
view > utility window > IP catalog
in IP catalog side bar: library > clocks; pll and resets > PLL
double click altpll, this opens a window
name your file, select verilog, click ok, this opens the megawizard
under speed grade leave as any?
(I am unclear on this step, any support or explanation of speed grade would be greatly appreciated. regardless, leaving it as any seems to work just fine)
"what is the input frequency of inclk0 input?" -> choose the clock frequency of the actual clock on your board, mine is 50MHz
click next, unselect areset (this will just allow you to control whether or not you want the clock to run)
click next a bunch of times, the defaults are fine, until you reach c0 - core/external output clock
select the "enter output clock frequency" radio button, then choose your desired output clock frequency
(keep in mind there are upper and lower inputs, and I have no idea what they are exactly.. but it wont accept values higher than 1000MHz, or values lower than 0.01MHz in my case)
I selected a value of 40MHz since I am doing this for a VGA display signal
http://tinyvga.com/vga-timing/800x600@60Hzclick next, if you wanted multiple clock signals, you can use the following 4 pages to set them up in the same way you set up the first
otherwise, click next past all of them until you reach the summary page
now what files you want here is up to you but I just deselected everything
then click finish, and then okay to the next window that pops up
okay, now you should have a .v file in your project with a module in it that you can pass your 50MHz clock into and output your desired clock frequency
in order to use it, go to your project navigator, click the dropdown and select files
then click the little dropdown arrow next to the item with the name of your module
in here there should be a verilog file. you can open it and take a look if youd like, pretty wild lookin in there
now in your top module you will need to instantiate this module, connecting your clock to the input pin, the other two pins are c0 and then a line called locked. c0 is your clock
locked is an indication of whether the clock is running or not
if you had left the "areset" option checked, you would have a signal which can control when the clock is running!
this signal requires a logical low to start
if you omit this option the clock will always run
I modified the blink code to use this new clock
module blink (clk, reset, LED);
input clk, reset;
output [1:0] LED;
reg [31:0] counter;
reg LED_status;
wire clk2;
pllTest2 pll(reset, clk, clk2, LED[0]);
initial begin
counter <= 32'b0;
LED_status <= 1'b0;
end
always @ (posedge clk2)
begin
counter <= counter + 1'b1;
if (counter > 40000000)
begin
LED_status <= !LED_status;
counter <= 32'b0;
end
end
assign LED[1] = LED_status;
endmodule 
