Show Posts

This section allows you to view all posts made by this member. Note that you can only see posts made in areas you currently have access to.

Messages - Noob 2174

Pages: [1]
FPGA / Phase locked loop
« on: June 02, 2020, 05:28:51 PM »
I have made myself a phase locked loop (PLL) using my cyclone iv FPGA
Here is what I did

view > utility window > IP catalog
in IP catalog side bar: library > clocks; pll and resets > PLL
double click altpll, this opens a window
name your file, select verilog, click ok, this opens the megawizard

under speed grade leave as any?
(I am unclear on this step, any support or explanation of speed grade would be greatly appreciated. regardless, leaving it as any seems to work just fine)

"what is the input frequency of inclk0 input?" -> choose the clock frequency of the actual clock on your board, mine is 50MHz
click next, unselect areset (this will just allow you to control whether or not  you want the clock to run)
click next a bunch of times, the defaults are fine, until you reach c0 - core/external output clock
select the "enter output clock frequency" radio button, then choose your desired output clock frequency
(keep in mind there are upper and lower inputs, and I have no idea what they are exactly.. but it wont accept values higher than 1000MHz, or values lower than 0.01MHz in my case)

I selected a value of 40MHz since I am doing this for a VGA display signal

click next, if you wanted multiple clock signals, you can use the following 4 pages to set them up in the same way you set up the first
otherwise, click next past all of them until you reach the summary page

now what files you want here is up to you but I just deselected everything
then click finish, and then okay to the next window that pops up

okay, now you should have a .v file in your project with a module in it that you can pass your 50MHz clock into and output your desired clock frequency
in order to use it, go to your project navigator, click the dropdown and select files
then click the little dropdown arrow next to the item with the name of your module
in here there should be a verilog file. you can open it and take a look if youd like, pretty wild lookin in there

now in your top module you will need to instantiate this module, connecting your clock to the input pin, the other two pins are c0 and then a line called locked. c0 is your clock
locked is an indication of whether the clock is running or not

if you had left the "areset" option checked, you would have a signal which can control when the clock is running!
this signal requires a logical low to start
if you omit this option the clock will always run

I modified the blink code to use this new clock

Code: [Select]
module blink (clk, reset, LED);

input clk, reset;
output [1:0] LED;

reg [31:0] counter;
reg LED_status;

wire clk2;

pllTest2 pll(reset, clk, clk2, LED[0]);

initial begin
counter <= 32'b0;
LED_status <= 1'b0;

always @ (posedge clk2)
counter <= counter + 1'b1;
if (counter > 40000000)
LED_status <= !LED_status;
counter <= 32'b0;


assign LED[1] = LED_status;


FPGA / Re: Ptogramming ROM chip
« on: May 29, 2020, 02:51:21 PM »
What is up my friend! I figured it out!

I have been researching all night trying to figure out which chip stores the configuration in other fpga boards, and then trying to find it on this storm iv board. well looking at the board didnt help, but, looking at the block diagram gave me the answer I was looking for. This board uses an EPCS4 chip!

Here is the process I went through to program this chip:
(A process I learned from watching Ben Heck!

after compiling your design into a ".sof" file
click file, convert programming files, opening the convert programming files window
click the "programming file type" drop down and select "JTAG indirect configuration file (.jic)"
click the "..." icon next to the configuration device dropdown, opening a configuration device window
under device family select Cyclone IV E
in the configuration device tab select the "EPCS4" device and click OK
next, under input files to convert, click on "flash loader", then to the right, click on add device, which opens the "select devices" window
under device family again select Cyclone IV E
then select our specific cyclone device version under device name, "EP4CE6", click OK
next click "SOF Data" inside input files to convert, and click add file
choose the .sof file you want
click on the "yourdesign.sof" item under SOF data, and click the properties button
check the compression checkbox, click ok
finally, click generate!

now we need to open the programmer and upload this new file to our board!

click tools, programmer
first, delete any item that is already in here, we want it empty
click add file, find your ".jic" file, it should just be in the same place as your .sof file
click the "program/configure" checkbox
then click start

and that's it! you can now power cycle your device and your design will remain!
;)  8)

FPGA / Re: Ptogramming ROM chip
« on: May 29, 2020, 09:10:06 AM »
Yes, FPGAs will loose the synthesis when you rebgoot. You have to make a code taht will automatically get the synthesis from a flash memory. Placing the code into the flash memory of the FPGA is a bit tricky. Is usaully different for each chip. Maybe you can find a YouTube tutorial because I still don't have a video about that...

Alright I thought I would at least ask you about it since I have the exact same storm iv board as you.

I don't have this issue with my lattice boards. Their tool chain also seems to be a bit friendlier than the altera stuff.
I have a few "tiny FPGA" boards and they are very very easy to use. I personally would recommend those for beginners.

I have the AX2 and BX boards which I got from sparkfun

Thanks anyway!
If I figure it out I will share what I learned.

FPGA / Programming ROM chip (EPCS)
« on: May 29, 2020, 08:05:22 AM »
I followed the blink tutorial for the storm iv board, it works.
However, when I reset my board it goes back to the default design that it came with (the 7 segment displays counting from 0 to 9)
How can I flash the little ROM chip on the board so that my design stays when I reset it?


Pages: [1]